According to the german site TecChannel VIA's Marketing Manager Shane Dennison admitted that VIA is working on a solution to this known problem. The issue was first discussed by TecChannel in an article about PCI bus transfer rates when ATA133 controllers either onboard or as addon solutions were used. Chipsets based on Intel or SiS performed noticably higher than VIA products (up to 32%). Still unclear is which steps VIA will take to resolve the issue. Maybe a revised 4-in-1 driver will do or a BIOS update might be necessary. TecChannel also took a closer look at the unofficial PCI latency patch. More about that can be read under the read more option.
The PCI latency patch first appeared on VIAHardware.com an information website about PC hardware. The patch was offered in version 0.19. Intensive discussions about the usefulness of the patch started in the VIAHardware forums. Users reported about non-functionality of the patch, issues fixed, new issues arose and so on. To clear things up here is what this patch does: This patch is unofficial! It was developed by George Breese - a programmer from Networking Resources. The PCI Latency indicates the number of clock cycles, for which a PCI Busmaster device may stress the bus for itself, before it is again released. This minimum number of clocks is to prevent that the PCI performance sinks too heavily due to frequent aborts of the Burst phases. At the same time the Latency timer prevents the exclusive recourse of the PCI bus by only one device. After the PCI Latency time sequence during a Burst phase every other PCI DEVICE can request the bus. The Burst is then aborted immediately. The PCI latency patch now - among other things - alters the following settings through registers in the northbridge: Disables options PCI delay transaction and PCI master read caching -> register 70; bit 1 and 2 The Arbitration-Timer of the PCI controller is set to 96 cycles. Typical BIOS setting is 32 cycles. This option is meant to prevent the 686B Southbridge IDE bug. -> register 75; bit 0 to 2 or 0 to 3. The PCI controller latency timer is set to 0. The timer otherwise guarantees a certain number of clock cycles to the CPU if the PCI bus is addressed. -> register 0D Exclusion of the CPU from the PCI priority rotation. Normally CPU access to the PCI bus is guaranteed after up to three other devices had access to the bus. -> register 76; bits 4 and 5 These altered settings resulted in an improvement of burst rates up to the above mentioned 32%. You can try the patch for yourself. I recommend though to take a look at the forums (see above) first. Remember this not an official solution.
The PCI latency patch first appeared on VIAHardware.com an information website about PC hardware. The patch was offered in version 0.19. Intensive discussions about the usefulness of the patch started in the VIAHardware forums. Users reported about non-functionality of the patch, issues fixed, new issues arose and so on. To clear things up here is what this patch does: This patch is unofficial! It was developed by George Breese - a programmer from Networking Resources. The PCI Latency indicates the number of clock cycles, for which a PCI Busmaster device may stress the bus for itself, before it is again released. This minimum number of clocks is to prevent that the PCI performance sinks too heavily due to frequent aborts of the Burst phases. At the same time the Latency timer prevents the exclusive recourse of the PCI bus by only one device. After the PCI Latency time sequence during a Burst phase every other PCI DEVICE can request the bus. The Burst is then aborted immediately. The PCI latency patch now - among other things - alters the following settings through registers in the northbridge: Disables options PCI delay transaction and PCI master read caching -> register 70; bit 1 and 2 The Arbitration-Timer of the PCI controller is set to 96 cycles. Typical BIOS setting is 32 cycles. This option is meant to prevent the 686B Southbridge IDE bug. -> register 75; bit 0 to 2 or 0 to 3. The PCI controller latency timer is set to 0. The timer otherwise guarantees a certain number of clock cycles to the CPU if the PCI bus is addressed. -> register 0D Exclusion of the CPU from the PCI priority rotation. Normally CPU access to the PCI bus is guaranteed after up to three other devices had access to the bus. -> register 76; bits 4 and 5 These altered settings resulted in an improvement of burst rates up to the above mentioned 32%. You can try the patch for yourself. I recommend though to take a look at the forums (see above) first. Remember this not an official solution.
