On March 18th, 2003 the United States Patent and Trademark Office has issued patent #6,535,988 to Santa Clara based Intel Corp. Patent #6,535,988 describes a mechanism and method for detecting and deterring over-clocking of a system clock signal in a computer system. Intel claims in the background information that there may be a problem with resellers and / or distributors remarking processors at higher frequencies and then selling the processors as the higher speed part to charge for resale at higher prices. Furthermore the company goes on that overclocking a system (processor) clock frequency may also produce several problems, like bit errors and data corruptions. So be prepared for low level locked Intel processors in the future.
What is claimed is: 1. A mechanism for detecting and deterring over-clocking of a clock signal for use in a processor, comprising: a detection circuit adapted to detect over-clocking of a clock signal for use in the processor based on a reference signal; and a prevention circuit adapted to prevent over-clocking of said clock signal by limiting or reducing performance of the processor in response to detection of said over-clocking of said clock signal. 2. The mechanism as claimed in claim 1, wherein said detection circuit comprises: a quart crystal to generate said reference signal exhibiting a fixed clock frequency; a counter to count cycles of said clock signal relative to the clock of said reference signal and to produce a counter value; a comparator to determine whether said clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected. 3. The mechanism as claimed in claim 2, wherein said counter is clocked by said clock signal, and is set or reset to zero (0) by a rising edge of the clock of said reference signal. 4. The mechanism as claimed in claim 2, wherein said comparator determines said over-clocking condition when the counter value reaches a maximum allowed ratio, and an under-clocking condition when the counter value is below a minimum allowed ratio. 5. The mechanism as claimed in claim 1, wherein said detection circuit comprises: a ring oscillator to generate said reference signal exhibiting a fixed clock frequency; a counter to count cycles of said clock signal relative to the clock of said reference signal and to produce a counter value; a comparator to determine whether said clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected. 6. The mechanism as claimed in claim 1, wherein said prevention circuit is also adapted to prevent over-clocking of said clock signal by disabling operations of the processor as an alternative to limiting or reducing the performance of the processor, said prevention circuit comprising a power supply control logic device adapted to deactivate a power supply from attending to the processor and disables operations of the processor, in response to detection of said over-clocking of said clock signal. 7. The mechanism as claimed in claim 1, wherein said prevention circuit comprises a thermal control logic device adapted to assert a stop clock signal to the processor to halt the processor temporarily from operations, in response to detection of said over-clocking of said clock signal. 8. The mechanism as claimed in claim 1, wherein said prevention circuit comprises a frequency select device adapted to assert a frequency select signal to the processor to reduce an operation frequency of the processor, in response to detection of said over-clocking of said clock signal. View patent #6,535,988
What is claimed is: 1. A mechanism for detecting and deterring over-clocking of a clock signal for use in a processor, comprising: a detection circuit adapted to detect over-clocking of a clock signal for use in the processor based on a reference signal; and a prevention circuit adapted to prevent over-clocking of said clock signal by limiting or reducing performance of the processor in response to detection of said over-clocking of said clock signal. 2. The mechanism as claimed in claim 1, wherein said detection circuit comprises: a quart crystal to generate said reference signal exhibiting a fixed clock frequency; a counter to count cycles of said clock signal relative to the clock of said reference signal and to produce a counter value; a comparator to determine whether said clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected. 3. The mechanism as claimed in claim 2, wherein said counter is clocked by said clock signal, and is set or reset to zero (0) by a rising edge of the clock of said reference signal. 4. The mechanism as claimed in claim 2, wherein said comparator determines said over-clocking condition when the counter value reaches a maximum allowed ratio, and an under-clocking condition when the counter value is below a minimum allowed ratio. 5. The mechanism as claimed in claim 1, wherein said detection circuit comprises: a ring oscillator to generate said reference signal exhibiting a fixed clock frequency; a counter to count cycles of said clock signal relative to the clock of said reference signal and to produce a counter value; a comparator to determine whether said clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected. 6. The mechanism as claimed in claim 1, wherein said prevention circuit is also adapted to prevent over-clocking of said clock signal by disabling operations of the processor as an alternative to limiting or reducing the performance of the processor, said prevention circuit comprising a power supply control logic device adapted to deactivate a power supply from attending to the processor and disables operations of the processor, in response to detection of said over-clocking of said clock signal. 7. The mechanism as claimed in claim 1, wherein said prevention circuit comprises a thermal control logic device adapted to assert a stop clock signal to the processor to halt the processor temporarily from operations, in response to detection of said over-clocking of said clock signal. 8. The mechanism as claimed in claim 1, wherein said prevention circuit comprises a frequency select device adapted to assert a frequency select signal to the processor to reduce an operation frequency of the processor, in response to detection of said over-clocking of said clock signal. View patent #6,535,988
