Aims to remove bottlenecks from incumbent ringbus architecture. A fully-fledged processor is far more than just an aggregation of cores. There needs to be a means of connecting the cores to external memory, IO - usually through PCIe or QPI - and the supporting L3 cache. In Intel-speak, this is known as connecting the core to the uncore.

Various companies use an in-house topology that forms this interconnect. In the case of Intel, as it pertains to Xeon processors, this core-wide interconnect is known as the ringbus architecture that was prevalent with the Sandy Bridge architecture way back in 2011.