Kentron Technologies, Inc., a privately held company, announced that VIA Technologies, Inc., a leading innovator and developer of silicon chip technologies and PC platform solutions, and S3 Graphics, Inc., have licensed the QBM technology. The QBM controller interface license provides VIA and S3 Graphics with the necessary IP coverage to incorporate QBM into their line of PC, Workstation and Server core logic chipset solutions. The QBM technology doubles the speed of Double Data Rate (DDR) memory devices, maintains the existing 64-bit bus structure common in today?s general purpose computing systems and meets the marketplace?s requirement for low cost memory modules. Using existing DDRI devices, the technology provides DDRII speeds, cost savings and a dramatic performance improvement over DDR333, DDR400, future DDRII modules, and other more expensive, non-DDR compatible memory technologies. Read more...
This license marks the first time that PC based systems will be able to interface to the high speed DDR533 and DDR667 modules featuring QBM technology. New systems using QBM enabled chipsets from VIA and S3 Graphics will combine the fastest speed memory in the industry with the fastest processor front side bus speeds and maintain backward compatibility with today?s DDR infrastructure. "VIA is committed to delivering higher performance chipset solutions to the marketplace while minimizing cost impact on our customers," said Chewei Lin, Vice President of Product Marketing, VIA Technologies, Inc. "Kentron?s leading edge QBM memory technology will enable us to strengthen our position as the market leader in providing high-performance chipsets and, at the same time, exploit all the potential of the existing DDR SDRAM infrastructure." Technical Background: The QBM technology consists of at least two independent DDR memory devices running simultaneously. Both memory devices share the same command and address lines and each device receives a pair of differential clock signals at frequency to control all synchronous operations. The clock of the first memory device is in-phase with the controller clock, while the second device?s clock has a phase difference of 90-degrees from the first clock (created by the on DIMM PLL). The result is the data packed in 4-bits per cycle (double DDR I) versus today?s DDR at 2-bits per cycle. DDR Module Differences: The main difference between an unbuffered DDR I DIMM and an unbuffered QBM DIMM is that the QBM DIMM (non-ECC mode) has eight, low cost QBM-10R switches and one PLL. These components are in standard packages and require no special manufacturing considerations. Both DDR I and QBM DIMMs fit into standard 184-pin connectors unlike the 240-pin DDR II which is not backward compatible with DDR I. Availability: QBM533 (PC4200) Modules will be available for sampling in December of 2002 with production modules becoming available in Q1 2003. QBM667 (PC5400) modules will be available in Q2 of 2003 to coincide with the release of 667 FSB Processors. QBM800 (PC6400) modules based on DDR I-400 devices will be available in the second half of 2003 followed by DDRII based QBM modules ranging from QBM800 (PC6400) ? QBM1066 (PC8500) in the 2004-2005 timeframe.
This license marks the first time that PC based systems will be able to interface to the high speed DDR533 and DDR667 modules featuring QBM technology. New systems using QBM enabled chipsets from VIA and S3 Graphics will combine the fastest speed memory in the industry with the fastest processor front side bus speeds and maintain backward compatibility with today?s DDR infrastructure. "VIA is committed to delivering higher performance chipset solutions to the marketplace while minimizing cost impact on our customers," said Chewei Lin, Vice President of Product Marketing, VIA Technologies, Inc. "Kentron?s leading edge QBM memory technology will enable us to strengthen our position as the market leader in providing high-performance chipsets and, at the same time, exploit all the potential of the existing DDR SDRAM infrastructure." Technical Background: The QBM technology consists of at least two independent DDR memory devices running simultaneously. Both memory devices share the same command and address lines and each device receives a pair of differential clock signals at frequency to control all synchronous operations. The clock of the first memory device is in-phase with the controller clock, while the second device?s clock has a phase difference of 90-degrees from the first clock (created by the on DIMM PLL). The result is the data packed in 4-bits per cycle (double DDR I) versus today?s DDR at 2-bits per cycle. DDR Module Differences: The main difference between an unbuffered DDR I DIMM and an unbuffered QBM DIMM is that the QBM DIMM (non-ECC mode) has eight, low cost QBM-10R switches and one PLL. These components are in standard packages and require no special manufacturing considerations. Both DDR I and QBM DIMMs fit into standard 184-pin connectors unlike the 240-pin DDR II which is not backward compatible with DDR I. Availability: QBM533 (PC4200) Modules will be available for sampling in December of 2002 with production modules becoming available in Q1 2003. QBM667 (PC5400) modules will be available in Q2 of 2003 to coincide with the release of 667 FSB Processors. QBM800 (PC6400) modules based on DDR I-400 devices will be available in the second half of 2003 followed by DDRII based QBM modules ranging from QBM800 (PC6400) ? QBM1066 (PC8500) in the 2004-2005 timeframe.
