Synopsys, Inc. is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Their latest press release discloses first details of an upcoming ATI VPU (R400?).
Excerpt: Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced that ATI Research, a subsidiary of ATI Technologies, Inc., has adopted Synopsys' DFT Compiler? SoCBIST to implement the design-for-test architecture for its upcoming next-generation visual processor. SoCBIST is an extension to DFT Compiler, a key component of Synopsys' Galaxy? Design Platform. By using SoCBIST, ATI is able to improve test quality and reduce test cost for one of their most important designs. ATI's visual processing unit (VPU) has more than 200 million transistors of digital logic. A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.13 micron process geometries and below. Using basic scan methods, excellent delay test requires up to 6X more tester time than required for stuck-at faults, which already is at an unacceptable cost of test. Source: Synopsys
Excerpt: Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced that ATI Research, a subsidiary of ATI Technologies, Inc., has adopted Synopsys' DFT Compiler? SoCBIST to implement the design-for-test architecture for its upcoming next-generation visual processor. SoCBIST is an extension to DFT Compiler, a key component of Synopsys' Galaxy? Design Platform. By using SoCBIST, ATI is able to improve test quality and reduce test cost for one of their most important designs. ATI's visual processing unit (VPU) has more than 200 million transistors of digital logic. A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.13 micron process geometries and below. Using basic scan methods, excellent delay test requires up to 6X more tester time than required for stuck-at faults, which already is at an unacceptable cost of test. Source: Synopsys
