Intel Corp. gave a bit of information away on their upcoming processor on the International Solid State Circuits Conference last weekend. Compared to the current Itanium CPU McKinley based processors will feature an additional L3 cache on die as well as faster bus speeds.
McKinley will be a 64bit processor set to overcome the current Itanium build. More technical details...
The McKinley will feature 3Mb of Level 3 cache, along with 256K of level 2 cache and 32K of level 1 cache. This compares to 4MB of onboard level 3 cache, 96K of level 2 cache and 32K of level one cache in the first generation Itanium. At the same time, the system bus in McKinley will be 128 bits wide, offering 6.4GB/s and running at 400MHz. This compares to its predecessor which offered 2.1GB/s, was 64 bits wide and ran at 266MHz. Intel claims that together with an increase in clock speed to 1GHz from 800MHz on the original Itanium, the changes will help increase performance by one and a half to two times, without the need to recompile software. Optimizing applications could eke a little more performance the firm said. The total size of the chip will be 421 square millimeters, and it will carry 221 million transistors, including the on-die level 3 cache. The previous generation carried 25 million, although the off-die cache accounted for a further 300 million. Other changes include a reduction in the number of pipeline stages from 10 to eight. Two further execution units have been added. Source: Computer Business Review Online
McKinley will be a 64bit processor set to overcome the current Itanium build. More technical details...
The McKinley will feature 3Mb of Level 3 cache, along with 256K of level 2 cache and 32K of level 1 cache. This compares to 4MB of onboard level 3 cache, 96K of level 2 cache and 32K of level one cache in the first generation Itanium. At the same time, the system bus in McKinley will be 128 bits wide, offering 6.4GB/s and running at 400MHz. This compares to its predecessor which offered 2.1GB/s, was 64 bits wide and ran at 266MHz. Intel claims that together with an increase in clock speed to 1GHz from 800MHz on the original Itanium, the changes will help increase performance by one and a half to two times, without the need to recompile software. Optimizing applications could eke a little more performance the firm said. The total size of the chip will be 421 square millimeters, and it will carry 221 million transistors, including the on-die level 3 cache. The previous generation carried 25 million, although the off-die cache accounted for a further 300 million. Other changes include a reduction in the number of pipeline stages from 10 to eight. Two further execution units have been added. Source: Computer Business Review Online
