Intel Corporation revealed new details of its advanced "tri-gate" transistor design this week at the 2003 Symposia of VLSI Technology and Circuits in Kyoto, Japan and said that the tri-gate transistor is moving from research to the development phase. The design of this novel three-dimensional (3-D) transistor will allow the company to continue to drive Moore's Law and to deliver higher performance, lower power processors in the future. Fast transistors are one of the key building blocks of high-performance microprocessors. Since originally announced last year, Intel researchers have successfully shrunk the size of the tri-gate transistor (measured by the gate length) from 60 nanometers (nm) to 30 nm. Transistors with a smaller gate switch on and off faster, ultimately enabling faster microprocessors.

Intel's tri-gate transistor employs a novel 3-D gate structure, like a raised plateau with vertical sides, which allows electrical signals to be sent along the top of the transistor gate and along both vertical sidewalls. This effectively triples the space available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more area. This gives the tri-gate transistor much higher performance than today's planar (flat) transistors. Intel's tri-gate transistor is designed so that it can be manufactured in high volume, a factor that will be key in moving it from the development stage into production. The tri-gate transistor design also addresses the growing current leakage problem that the industry faces as CMOS devices are made ever smaller. Due to its unique structure, the tri-gate transistor's leakage is far less than that of a planar transistor of the same size. Intel has moved the tri-gate transistor design from research to the development phase, and experimental devices have been successfully manufactured at Intel's 300-mm wafer fabrication facility (Fab D1C) in Hillsboro, Ore. Source: Intel