3Dlabs, Inc. Ltd. today announced a ground-breaking Visual Processing Architecture that combines the architectural strengths and programmability of general-purpose CPUs with extreme levels of hardware parallelism. This architecture, which has been in development for the past two years and has significant patents pending, enables advanced software rendering techniques to be accelerated in real time to produce interactive imagery with stunning levels of realism. 3Dlabs expects to ship board-level products based on the first Visual Processing Unit (VPU), a chip codenamed the P10, during the third quarter of 2002.



3Dlabs' Visual Processing Architecture implements an optimized graphics pipeline, replacing previously inflexible pipeline stages with highly programmable SIMD (single instruction, multiple data) processor arrays. The P10 VPU combines over 200 SIMD processors throughout its geometry, texture and pixel processing pipeline stages to deliver over 170Gflops and one TeraOp of programmable graphics performance together with a full 256-bit DDR memory interface for up to 20GBytes/sec of memory bandwidth. This sums up to the following specs: 0.15-micron manufacturing process 76Mio transistors 4 pixel rendering pipelines, can process two textures per pipeline 256-bit DDR memory interface (up to 20GB/s of memory bandwidth w/ 312.5MHz DDR) up to 256MB of memory on-board AGP 4X support Full DX8 pixel and vertex shader support Source: 3Dlabs

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